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| SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 SY10 * INTRODUCTION Date: August 30, 2002 The SY10 - an accurate time and frequency source that had been designed as a subsystem level module. The module is designed to work within ATM, SONET, SDH, and wireless systems where synchronization is vital. The SY10 is an excellent synchronization solution for timing, with jitter and wander compliance per the specified within ITU-T Recommendations G.812/G.813 and Bellcore GR-1244-CORE. The SY10 is an enhanced version of SY01 and is designed for Stratum 3 and Stratum 3E, but also holds certain features that can make it useful for SONET Minimum Clock (SMC) or other kinds of system clocks. * FEATURES A synchronization solution for timing, jitter and wander concerns in a single module. Complies with ITU-T Recommendations G.812/813 and Bellcore GR-1244-CORE for Stratum 3 and Stratum 3E applications. Supports modes of operation: Locked, Holdover and Free-run. Accepts reference inputs from up to six independent sources from 8KHz to 77.76MHz Provides up to 3 output from 8KHz to 77.76MHz (Two user select and one fixed at 8KHz) Loop filtering utilizing specific software application in the digital signal processor (DSP). Continuously monitors and evaluate input reference signals. Phase build-out for output clock. Creates a history buffer for Holdover mode operation. Alarm and status signals and messages. Host interface SPI for configuring and remote monitoring. Supports Master/Slave configuration of two SY10 with minimum phase error between two clocks. Provides "hit-less" switching during switching between the clocks. Pin compatible with 18 pins SY01 module. Small dimensions of 1.82 x 1.82 x 0.7 inch. (0.60 inch with no mechanical cover) * APPLICATION The SY10, a Synchronous Equipment Clock (SEC), fulfills clock regeneration function for STRATUM 3 and 3E equipment for: ATM, SDH, PDH, and SONET networks. It was designed for network system manufacturers such as: Access Switches, Core Switches, Cross Connects, Digital Multiplexers-Exchangers, and SDH/SONET equipment. The unit is also suitable for PCS, WLL, and Wireless Base Stations. Wherever a Timing unit with high performance specifications is required, the SY10 can be embedded within the network system and provide all necessary frequencies and interfaces. RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 1 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 Alarms and Statuses Ex.Ref.1 Ex.Ref.2 Ex.Ref.3 Ex.Ref.4 Ex.Ref.5 Ex.Ref.6 OCXO MUX, FPD, Counters & Logic OUT 3 DSP (RAM, FLASH) DDS Output PLL Synthesizer OUT 2 OUT 1 Control Inputs SPI JTAG Figure 1. - The functional block diagram of SY10. * DESCRIPTION The SY10 synchronization module is a Digital PLL (DPLL), which utilizes application specific software in the digital signal processor (DSP). The DSP is complemented by fast hardware logic (FPGA) where all multiplexers, counters, dividers, phase detectors, output frequency converters and other control logic circuits are completely implemented. The functional block diagram with maximum configuration is shown in figure 1. The module has three phase lock loop - primary PLL, secondary and utility PLL. The primary PLL utilizes a Direct Digital Synthesis (DDS) technique combined with a high stability OCXO in order to provide an accurate and fast DPLL response and eliminates the requirement for an OCXO with high pullability. The primary loop is a low bandwidth loop that filters a major part of the wander and the jitter at the input. The output of the primary PLL is connected to the secondary PLL synthesizer that is also a DPLL but with a wider loop bandwidth. The secondary PLL loop has also another input that comes from the SEC IN pin. Depending on the master-slave mode, the secondary loop utilizes either one of the inputs. The output of secondary PLL is connected to the utility PLL that is an analog phase lock loop. The outputs of secondary and utility PLL provide three independent output signals. The SPI serial communication interface provides a flow of messages between the module and a host processor. The JTAG interface provides an easy access for future software upgrade re-programming without removing the module from the system. The SY10 software provides several features such as: switching between the references inputs on the basis of monitoring and estimation of the input signals and internal state diagram; real time calculation of the filtering algorithm for jitter and wander in according to the approved standards; alarm, status and messaging functions using output pins and serial communication port. For other configurations, please contact Raltron. " The module operates in the following three timing modes: Free-run In this mode, the unit is unlocked to either of the inputs. The accuracy of the output frequencies in this mode is 4.6ppm. Free-run mode is typically used when a master clock source is required, not valid history of data for the Holdover mode, or immediately following system power-up before network synchronization is achieved. In the Freerun Mode, the SY10 provides timing and synchronization signals that are based on the accuracy of on-board oscillators only, and are not synchronized to the reference signals. Holdover RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 2 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 In this mode, the module has lost its reference inputs and is utilizing stored timing data, called history, to control the output frequency. Holdover Mode is typically used while the network synchronization is temporarily disrupted. In Holdover Mode, the SY10 provides timing, based on data from the history buffer, while unlocked to an external reference signal. The history data is determined while the device is locked to an external reference signal. The stability of the output signal in holdover mode depends primarily on the stability of on-board oscillator and environment effects where the clock is mounted. The SY10 uses an OCXO as an on-board oscillator but other types of oscillators are available. Locked to Reference In this mode, the output of the module is phase locked to any of input references. The output frequency tracks the selected input reference. The "Locked to Reference Modes" is typically used when a slave clock source is synchronized to the network. In these modes, the SY10 provides timing signals, which are synchronized, to one of six references inputs (REF1 to REF6). The input reference signals may have a variety of nominal frequencies, which are typically specified by the end user. When the modes are selected the unit goes through a reference evaluation, and then a frequency acquisition, and finally to phase locking. Local Reference Oscillator Depending on the type of clock, a local reference oscillator is selected. For example: for a Stratum 3E type of clock, the local oscillator is a high stability SC-cut OCXO that meets this standard requirements for frequency drift and jitter noise. Input References The SY10 module accepts six input references EX REF1 to EX REF6. End users can specify the frequencies within a range of 8 kHz to 77.76 MHz. The input reference signals are HCMOS/TTL levels with timing characteristic in accordance with Bellcore GR-1244-core 3.2.1.R3-1 or equivalent standards. Please note that the end user must specify the input frequencies at the time of order. Monitoring and Evaluation of the Input References Using an advanced algorithm the input references are continuously monitored and evaluated by the module. There are three techniques used in the algorithm for each of reference, presence of the reference, frequency offset during the time when the unit is phase locked to the reference, and frequency offset when the unit in not phase locked to the reference. The SY10 rejects all reference signals whose frequency accuracy is offset by more than 13 PPM. At any given event that requires a switching in the operation mode, the timing module unit performs a reference evaluation test of the new target reference. Since such evaluation is a continuous process, the switching takes very short time (typically less then a second). Providing a successful evaluation, the unit switches to frequency and phase locking mode. On the other hand, if the reference was not qualified the unit switches to a holdover mode. Filtering in the DPLL The SY10 dynamically changes its loop bandwidth according to the status of the DPLL. In the primary PLL there are five stages that the DPLL goes through before phase lock mode is achieved. The first stage is frequency acquisition that takes place until the frequency becomes equal to the reference. The second stage is the phase acquisition stage that takes place until a new phase reference is acquired. The other stages are tracking stages (1, 2 and 3) (hint: the DPLL is locked and tracks the phase reference with a very low loop bandwidth). This method of three tracking stages ensures minimum locking time and minimum phase jumps and shifts during acquisition or transition. It also provides phase build-out during switching or rearrangement. The secondary PLL operates similarly to the primary PLL with an exception of a wider bandwidth (hint: it has only three stages) - the first is frequency acquisition, second is phase acquisition and third one is tracking mode. Please see detail in state diagram. History Buffer for HOLDOVER mode Frequency and timing data is continuously collected in the history buffer during the time when the unit is locked to any of the input references. The history buffer is actually a circular buffer in memory that keeps valid data for HOLDOVER mode during the last 90 seconds of operation. When the SY10 enters to HOLDOVER mode the data RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 3 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 from the buffer is validated and processed. The history buffer can be cleared by writing one to bit HLRST in CFG2 register. Output Signals The SY10 module provides three output signals OUT, OPT OUT1 and OPT OUT2. The outputs are generated by the internal oscillators VCXO and scaled by the output frequency converters. Two VCXO oscillators can be used per module providing two independent frequency types and the third one (OPT OUT2) is derived from one of them. The performance of the module significantly depends on the output oscillator and special care is taken to define their specifications. The used VCXO are high quality crystal oscillators with very low output jitter. The frequency of the oscillator is specified according to the network application where the SY10 will be used. The frequency converters divide signal from the oscillator to the specified frequencies. Indications The SY10 provides detailed monitoring and indication of operation of the unit. Two types of monitoring and status indicating are provided: Visual indication: Using ten on board color mounted LED's that indicate the operating mode of the SY10. The LED indicators are mainly placed for system troubleshooting, and testing. Electronic indications: Using ten digital outputs that report status and alarms from the SY10. These alarms are mainly used for communication between the module and network equipment. - The internal LED indicators are: Signal Holdover REF1 REF2 REF3:. REF4: REF5 REF6 FREERUN UNLOCK ALARM LED super light red LED, ON when the module is in holdover mode. green LED, ON when the module is locked to reference 1. green LED, ON when the module is locked to reference 2. green LED, ON when the module is locked to reference 3 green LED, ON when the module is locked to reference 4. green LED, ON when the module is locked to reference 5. green LED, ON when the module is locked to reference 6. orange LED, ON when the unit is in free running mode. red LED, ON when the module is not locked to the selected reference signal. red LED, ON when there is an alarm in the module RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 4 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 Control Several controls pins are available for the user to control the operation of the SY10 Primary PLL. The three external inputs CNT1, CNT2 and CNT3 provide the feature to change the state of operation. Below, the truth table shows behavior of the SY10 module according to the control inputs states. CNT3 0 0 0 0 1 1 1 1 CNT2 0 0 1 1 0 0 1 1 CNT1 0 1 0 1 0 1 0 1 MODE OF OPERATION Free-run Locked to REF1 Locked to REF2 Holdover Locked to REF3 Locked to REF4 Locked to REF5 Locked to REF6 To change the operation of Secondary PLL (Master-Slave) can be change using MS/FR control pin. MODE OF OPERATION 1 (or open) Master (default) 0 Slave see explanation about MS/FR below. MS/FR The state of operation can be set and changed also using serial communication port, please see below. The SY10 State Machine - Primary PLL The state machine of SY10 module can be controlled using one of two interfaces: 1) three external control pins CNT1, CNT2 and CNT3. 2) setting bits (CON0, CON1, CON2 and CON3) in CFG1 register using serial peripheral interface (SPI). After the reset the module is set to use three external control pins for control function but user can change it by setting bit UI in register CFG1. By setting the UI bit to 1 the module ignores states of the control pins and use bits in CFG1 register for state engine control. On the figure below is shown simplified stated diagram of SY10 module. 1 FREE RUN 4 5 7 9 11 FREQ. and PHASE LOCKING 2 3 14 8 10 6 REFERENCE SWITCHING 12 HOLDOVER 13 Figure 2 - The SY10 state diagram - Primary PLL. RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 5 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 1) (FREERUN) The path 1 runs until control signals (CNT1,2,3 pins or CON0,1,2,3 bits in CFG1 register) are set to zero or there is no valid history available on the acquisition buffer for the holdover. 2) (FREERUN_ REFERENCE_SWITCHING) The path 2 runs when there was any change at control signals. 3) (REFERENCE_SWITCHING_FREERUN) The path 3 runs when the control signals were changed to zero - the free-run mode was selected. 4) (REFERENCE_SWITCHING) The path 4 runs until appropriate reference was selected. If the unit is in Auto Switching mode (bit AUTOEN in CFG2 register set to 1) the module will switch in the following conditions: 1) if a reference that was selected by control signals, 2) if the selected reference is not available it will switch based on Priority Table (registers PR1 - PR4). 3) if any of the references are not available it will go to holdover (path 8) If the unit is in Manual Switching mode (bit AUTOEN in CFG2 register set to 0) the module will switch in following conditions: 1) if a reference that was selected by control signals, 2) if the selected reference is not available it will go to holdover (path 8) 5) (FREQ&PHASE_LOCKING_FREERUN) The path 5 runs when the control signals were changed to zero - the free-run mode was selected. 6) (HOLDOVER_FREERUN) The path 6 runs when the control signasl were changed to zero - the free-run mode was selected or there is no valid history available on the acquisition buffer for the holdover. 7) (REFERENCE_SWITCHING_FREQ&PHASE_LOCKING) The path 7 runs when the reference switching was successfully finished - a reference was qualified and no changes at control signals. 8) (REFERENCE_SWITCHING_HOLDOVER) The path 8 runs if the following conditions: 1) if control signals were changed to one (0011) - the holdover mode was selected. 2) if the module is in Auto Switching mode (bit AUTOEN in CFG2 register set to 1) the module will switch to the holdover if none of the reference are available. 3) if the module is in Manual Switching mode (bit AUTOEN in CFG2 register set to 0) and selected reference was not qualified or reference was lost during process of evaluation. 9) (FREQ&PHASE_LOCKING_REFERENCE_SWITCHING) The path 9 runs in the following conditions: 1) if another reference was selected changing control signals. 2) if the module is in Auto Switching mode (bit AUTOEN in CFG2 register set to 1) the module will switch to the reference switching if at least one of the references is available and when the currently selected reference is failing. 3) if the unit was set to operate in Revertive mode (bit REVEN in CFG2 register is set to 1) and previously lost reference is back the module will switch to reuse the same reference. 10) (HOLDOVER_ REFERENCE_SWITCHING) The path 10 runs in the following conditions: 1) current selected reference was reacquired or if the other reference was selected changing control signals. 2) if the unit was set to operate in Revertive mode (bit REVEN in CFG2 register is set to 1) and previously lost reference is back the module will switch to reuse the same reference. RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 6 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 11) (FREQ&PHASE_LOCKING) The path 11 runs until the frequency acquisition or the phase locking is in progress with no changes at control pins. The module goes through a few intermediate states in order to accomplish phase tracking. There are three basic intermediate steps that include frequency acquiring, phase acquisition and tracking. Tracking can have additional steps depending of the bandwidth to be achieved. 12) (HOLDOVER) The path 12 runs until the holdover mode is in progress with no changes at control signals. 13) (FREQ&PHASE_LOCKING_ HOLDOVER) The path 13 runs in following conditions: 1) if the used reference was lost or was detected bad, 2) if the control signals were changed to one (0011) - the holdover mode was selected. 14) (FREERUN_HOLDOVER) The path 14 runs only if the control signals were changed to one (0011) and valid history buffer for holdover operation is available - the holdover mode was selected. SY10 Master-Slave Operation - Secondary PLL In systems where clock redundancy is required it is possible to connect two SY10 - such connection shown at the figure below. The module has two pins dedicated for this feature - MS/FR and SEC IN. The MS/FR control input selects if the module will operate as master (logic high) or slave in the system. The SEC IN is input for signal that comes from another clock module. In the system always clock "one" operates as master and the second one as slave clock. When operating as a slave the output of SY10 also tracks the master so it provides minimum phase difference between the two clocks. This is very useful as it makes easier "hitless" switching of references. The Master-Slave control can also be done using SPI communication setting the bit MS in register CFGREG1. Please see more in Memory Mapped Registers section. The typical Master-Slave connection block diagram is show on figure below. OUT (Pin 10) M/S SY10 1 SEC IN (Pin 25) M/S SEC IN (Pin 25) SY10 2 OUT (Pin 10) Figure 3. - The Master - Slave connection of two SY10. The state machine of SY10 Master -Slave operation module can be controlled using one of two interfaces: 3) one external control pin MS/FR. 4) setting MS bit in CFG1 register using serial peripheral interface (SPI). After the reset the module is set to use the external control pin for control function but user can change it by setting bit UI in register CFG1. By setting the UI bit to 1 the module ignores states of the control pins and use bits in CFG1 register for state engine control. On the figure below is shown simplified stated diagram of SY10 Master -Slave operation. RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 7 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 1 MASTER 3 2 4 SLAVE Figure 4. - The SY10 Master - Slave state diagram 1. (MASTER) The path 1 runs until control signals MS/FR is set to 1 (or MS bit in CFG1 register is set to 0) or there is no valid signal at SEC IN pin. No valid signal means either not present or not within frequency offset window. 2. (MASTER_SLAVE) The path 2 runs when there was a change at MS/FR control signal from 1 to 0 (or in case of MS bit in CFGREG1 from 0 to 1) and there is valid signal at SEC IN pin. 3. (SLAVE_MASTER) The path 3 runs when there was a change at MS/FR control signal from 0 to 1 (or in case of MS bit in CFGREG1 from 1 to 0) or there is no valid signal at SEC IN pin (signal disappeared). 4. (SLAVE) The path 4 runs until control signal MS/FR is set to 0 (or MS bit in CFG1 register is set to 1) and there is valid signal at SEC IN pin. see explanation below! MS/FR shared pin input Since the MS/FR control input pin shares the function special caution should be taken to drive it. The signal at MS/FR signal is sampled and processed by internal software and decisions are made using following: 1) To change status of Secondary PLL from Master to Slave using MS/FR the user have to change from 1 to 0 and keep the pin logic low for period longer then 100ms not communicating through SPI. If within that period of time MS/FR signal does not change level (0) and there is no clock signal at SCLK pin (no changing at SCLK for SPI communication) the operation will be changed from Master to Slave. No CLK signal SCLK Sampes MS/FR >100ms Change to SLAVE RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 8 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 2) To maintain Slave mode while still communicating through SPI signal MS/FR should be set high prior SCLK for no more then 100ms at any given time. Please see timing constrains for SPI communication. CLK signal SCLK Sampes MS/FR 100ms No Change 3) To change status of Secondary PLL from Slave to Master the signal MS/FR should be set to high (1) for period longer then 100ms not communicating through SPI. No CLK signal SCLK Sampes MS/FR >100ms Change to MASTER 4) To maintain Master mode while still communicating through SPI signal MS/FR should be set low during SCLK for no more then 100ms at any given time. Please see timing constrains for SPI communication. CLK signal SCLK Sampes MS/FR 100ms No Change Changing mode of operation can be done easier using SPI communication interface - please see next paragraph. For other configuration please contact Raltron Electronics Corp. RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 9 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 * SERIAL COMMUNICATION BUS - SPI The module can be configured, controlled and monitored using an on board serial communication port - SPI provided on the SY10. There are four pins available for this features SCLK, MS/FR, DIN and DOUT. The DIN and DOUT are ports used to transfer command and data in and out of the module. The SCLK is input used to clock the data transfer in and out of the module and MS/FR is shared pin that provides frame synch signal. The SY10 operates only as a slave device on SPI bus so the transfer of the data or command should be initiated by a microcontroller. The micro-controller can read or write to configuration registers and read only from status registers mapped internally into the SY10. Optionally the interface can be implemented in SPI. CPU SCLK DOUT DIN MS/FR SY10 Figure 9. - The SPI serial communication Communication Protocol for SPI The interface is synchronous peripheral interface (SPI), the master must to provide clock signal and initiate the communication cycles. There are read and write cycles and each communication cycle that consists of 16 clocks (8+8 bits). Data is latched every rising edge of clock input from most significant bit. The maximal allowed frequency for SCLK is 10MHz - tclk. Write data cycle The master sends to the module two bytes (2 x 8bits). First byte is always command byte. The second byte is the data byte contains information to write. Command byte data format: 7(MSB) R/W 6 X 5 A5 4 A4 3 A3 2 A2 1 A1 0(LSB) A0 - A5...A0 - Module register address please see the table 1. - R/W - Read (1) or Write (0) bit. - X - not used. Data byte format: 7(MSB) D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0(LSB) D0 - D7...D0 - Content to be written to the register addressed by A5:A0 Read data cycle The master sends to the module one-command byte and receives from module information byte (see 1.1 and 1.2). Command byte data format: 7(MSB) R/W 6 X 5 A5 4 A4 3 A3 2 A2 1 A1 0(LSB) A0 - A5...A0 - Module register address please see the table 1. - R/W - Read (1) or Write (0) bit. Data byte format: RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 10 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 7(MSB) D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0(LSB) D0 - D7-D0 - Content to be read from the module addressed by A5:A0 SPI Flowchart Entry point No of received bytes > 0? NO NO Received Address Valid? YES YES SPIStatus = ADDRESSERROR YES No of received bytes = 1? NO WRITE Command Read or Write? READ NO No of received bytes = 2? YES READ Fetch data from MMR to send out Command Read or Write? WRITE SPIStatus = OK SPIStatus = OVERFLOW NO Valid Data to write in MMR? YES Write Data in MMR SPIStatus = WRITEERROR Wait for the next byte Reset all SPIStatus = OK Figure 10. - The SPI flowchart. Timing diagrams RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 11 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 Please see below the timing diagram for a write and read cycles. Please note that DOUT is not a tri-state output. The minimum value for tclk is 100ns and time out tout is approximately 1sec. The SPI will latch data on input DIN and set data on output DOUT on every rising edge of SCLK however operation mode can be changed operates on request. Changes may include clock polarity, length of data etc. During the read cycle the master have to provide a pause between two bytes of minimum 1ms (twait 1ms). tclk SCLK tout tds DIN A4 A3 A2 tdh A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 DOUT MS/FR tfs tfh Figure 11. - Write cycle SPI 8-bit Parameter tclk - CLK tfs - Time to set FR prior CLK transition tfh - Time to hold FR after CLK transition tds-Time to set data prior CLK transition tdh - Time to hold data after CLK transition Min 100ns tclk/2 tclk/2 10ns 1ns Max tclk SCLK twait DIN DOUT A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 MS/FR Figure 12. - Read cycle SPI 8-bit RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 12 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 Memory Mapped Registers There are twenty-eight 8-bit registers accessible through the serial port: 12 registers to write and read data and 16 registers to only read data from module. See table 1 for memory map registers and their purpose. Addr. Read Write Name M 7 R23 R43 R63 x S7 S7 S7 S7 S7 S7 x x S41 x PS7 US3 S7 S7 UI X F7 P13 P33 F3 ST7 CID7 SID7 HID7 6 R22 R42 R62 x S6 S6 S6 S6 S6 S6 x x S40 x PS6 US2 S6 S6 X X F6 P12 P32 F2 ST6 CID6 SID6 HID6 5 R21 R41 R61 x S5 S5 S5 S5 S5 S5 x x S31 x PS5 US1 S5 S5 X P F5 P11 P31 F1 4 R20 R40 R60 x S4 S4 S4 S4 S4 S4 x x S30 x PS4 US0 S4 S4 MS F F4 P10 P30 F0 Format 3 R13 R33 R53 x S3 S3 S3 S3 S3 S3 x x S21 S61 PS3 SS3 S3 S3 CON3 R F3 P03 P23 B3 2 R12 R32 R52 x S2 S2 S2 S2 S2 S2 x x S20 S60 PS2 SS2 S2 S2 CON2 H F2 P02 P22 B2 1 R11 R31 R51 x S1 S1 S1 S1 S1 S1 x x S11 S51 PS1 SS1 S1 S1 CON1 R F1 P01 P21 B1 ST1 CID1 SID1 HID1 L 0 R10 R30 R50 x S0 S0 S0 S0 S0 S0 x x S10 S50 PS0 SS0 S0 S0 CON0 A F0 P00 P20 B0 ST0 CID0 SID0 HID0 Description 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y N N N N N N N N N N N N Y Y Y Y Y Y Y Y N N N N PR1 PR2 PR3 PR4 RFH1 RFH2 RFH3 RFH4 RFH5 RFH6 RFH7 RFH8 RST1 RST2 PSP1 PSP2 PMAX PMIN CFG1 CFG2 FA1 BW11 BW12 FB2 SST CID SID HID ST5 ST4 ST3 ST2 CID5 CID4 CID3 CID2 SID5 SID4 SID3 SID2 HID5 HID4 HID3 HID2 Table 1. Memory map registers. 4-bit priority for references 1-2 4-bit priority for references 3-4 4-bit priority for references 5-6 Not used Ref. 1 frequency shift in ppm Ref. 2 frequency shift in ppm Ref. 3 frequency shift in ppm Ref. 4 frequency shift in ppm Ref. 5 frequency shift in ppm Ref. 6 frequency shift in ppm Not used Not used References 1-4 status References 5-6 status Status of Primary PLL Status of Secondary and Utility PLL Maximum frequency pull in ppm Minimum frequency pull in ppm Configuration 1 Configuration 2 Frequency acquisition set for PLL1 Bandwidth 1 and 0 set for PLL1 Bandwidth 3 and 2 set for PLL1 Frequency acquisition (F) and Bandwidth track (B) for PLL2 SPI status register Customer ID register Software ID register Hardware ID register Reference Priority Registers (PR1 to PR4) - address 00-03h There are four registers PR1 - PR4 that specify priority during switching. Every reference has 4-bit priority so two references are defined per register. The priority means that the module in the event of loosing reference will lock to valid reference with higher priority available if bit AUTOEN of register CFG2 is set to one. The initial priority is set by module but can be overridden by customer. The highest priority is 1111b and the lowest priority is 0001b. If priority is set to zero (0000b) the reference will not be used in the module - the status will be "Reference present but not in use". - R10-R13 - defines reference 1 priority - R20-R23 - defines reference 2 priority - R30-R33 - defines reference 3 priority - R40-R43 - defines reference 4 priority - R50-R53 - defines reference 5 priority - R60-R63 - defines reference 6 priority The default values are: PR1:0x78h PR2:0x56h PR3:0x34h PR4:0x12h Frequency Shift Registers (RFH1-RFH8) - address 04-0Bh. RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 13 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 The registers indicate how far the references out of nominal frequency in parts per million (ppm). The resolution is 0.5ppm. The range is 63ppm. If the frequency above or below 63ppm range, the +63 or -63 is shown respectively and proper status indicated in Reference Status Registers. The format is 2-s compliment and for example if the content of RFS3 register is 11000111 then the third reference is: -28.5ppm 7(MSB) SIGN The default values are: RFH1: 0xFFh RFH2: 0xFFh RFH3: 0xFFh RFH4: 0XFFh RFH5: 0xFFh RFH6: 0xFFh RFH7: 0xFFh RFH8: 0xFFh 6 25 5 24 4 23 3 22 2 21 1 20 0(LSB) 2-1 Reference Status Registers (RST1-RST2) - address 0C-0Dh There are 2 reference status registers that hold information about status of references. Each reference has 2-bit status or each register keep statuses for four references. The possible statuses are: Binary number 00 01 10 11 Status Not Present Present Not in use Reference OK Description Reference not present or can not be evaluated Reference present but out of frequency range Reference present but not in use Reference present and in the frequency range - S10-S11 - defines status of reference 1 S20-S21 - defines status of reference 2 S30-S21 - defines status of reference 3 S40-S41 - defines status of reference 4 S50-S51 - defines status of reference 5 S60-S61 - defines status of reference 6 The default values are: RST1: 0x00h RST2: 0x00h PLL Status Registers (PSP1-PSP2) - address 0E-0Fh Register PSP1 indicates status of Primary PLL. In the register the 4 least significant bits indicate status of the PLL and the 4 most significant bits indicate reference in use in the loop. The possible statuses of Primary PLL are shown in PSP1: PS3-PS0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Status description PLL not locked. This status represents major error. Frequency Acquisition Phase Acquisition Tracking Bandwidth 0 Tracking Bandwidth 1 (SP1 only) Tracking Bandwidth 2 (SP1 only) Tracking Bandwidth 3 (SP1 only) Phase Build-out Holdover Free run The possible reference bits are: PS7-PS4 x000 x001 Status description No reference in use (module in Free run or Holdover) Reference 1 RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 14 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 x010 x011 x100 x101 x110 0xxx 1xxx Reference 2 Reference 3 Reference 4 Reference 5 Reference 6 Holdover History Buffer Not Available Holdover History Buffer Available Register PSP2 indicates status of Secondary PLL. In the register the 4 least significant bits indicate status of the Secondary PLL and the 4 most significant bits indicate status of the utility PLL if available. SS3-SS0 0000 0001 0010 0011 0100 0101 0110 Status description PLL not locked. This status represents major error. Frequency Acquisition operating as a master clock Phase Acquisition operating as a master clock Tracking Bandwidth operating as a master clock Frequency Acquisition operating as a slave clock Phase Acquisition using operating as a slave clock Tracking Bandwidth using operating as a slave clock The possible utility PLL status bits. US3-US0 0000 0001 The default values are: PSP1: 0x00h PSP2: 0x00h Status description Not locked Locked Frequency Pull Range Registers (PMAX and PMIN) - address 10-11h These registers specify the window of pull-in range and reference acceptance frequency window. The PMAX register specifies maximum frequency window that the module can be locked on and frequency beyond references will be rejected. The PMIN registers frequency window within references will be accepted. The PMAX must be greater then PMIN and both are positive numbers. The data format is unsigned binary 8-bit number, for example if the content of PMAX register is 00011110 and PMIN 00011010 then the pull in range is: 15ppm and reference acceptance is 13ppm: 7(MSB) 26 The default values are: PMAX: 0x1Eh PMIN: 0x1Ah 6 25 5 24 4 23 3 22 2 21 1 20 0(LSB) 2-1 Configuration Registers (CFG1 and CFG2) - address 12-13h Register CFG1 used to set clock mode of operation. The user can select which interface will be used to change the mode of operation by setting bit UI. If the UI bit in CFG1 register is set to 0 (default) the module will change the state in according to three input pins CNT1, CNT2 and CNT3. If the If the UI bit in CFG1 register is set to 1 the module will changed the state in according to four bits (CON0, CON1, CON2 and CON3) in CFG1 registers. There are 4 bits to set 10 modes of operation: CON3 0 0 0 0 0 0 CON2 0 0 0 0 1 1 CON1 0 0 1 1 0 0 CON0 0 1 0 1 0 1 Mode of operation Free-run Lock to Reference 1 Lock to Reference 2 Holdover Lock to Reference 3 Lock to Reference 4 RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 15 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 Lock to Reference 5 Lock to Reference 6 Not used Not used Other combinations are not supported and ignored. Bits 7 to 4 of CFG1 are reserved for future use and ignored in this set. Bit MS in CFG1 sets the module to Master - Slave operation, MS bit 0 (default) the module operates as Master and MS bit 1 the module operates as slave in condition that a signal at SEC IN (pin 25) is present. Register CFG2 used by customer to control behavior of the module for application needs. 7(MSB) X 6 X 5 PBD 4 FREV 3 RESET 2 HLRST 1 REVEN 0(LSB) AUTOEN AUTOEN - when set to logic high, enabling automatic switching to other reference in the event of loosing current reference according to priority set by registers PR1-PR4. When set to logic low, will not switch to other reference. REVEN - when set to high, will enable revertive operation. HLRST - when set to high, will erase previous operation history for holdover. RESET - when set to high, will initiate internal reset of the module. FREV - when set to high and if AUTOEN set to high will switch references based on their frequency offset (select the best of available). PBD - when set to high Phase Build Out is disabled. The default values are: CFG1: 0x00h CFG2: 0x00h Frequency Acquisition set for Primary PLL (FA1) - address 14h FA1 register determines the bandwidth during frequency acquisition of PLL. The values of FA0-7 represent frequency acquisition in Hz (0-256Hz). The default values are: FA1: 100 Bandwidth set registers for PLL1 (BW11, BW12) - address 15-16h BW11 and BW12 registers determine the tracking bandwidth of the primary PLL. There four sets of bits each one representing the corresponding tracking bandwidth. The table below shows the available combinations. Px3 0 0 0 Px2 0 0 0 Px1 0 0 1 Px0 0 1 0 Bandwidth NA 0.001Hz 0.01Hz RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 16 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 0 0 0 0 0 1 The default values are: BW11: 0x23h BW12: 0x01h 0 1 1 0 1 0 1 1 1 1 0 0 All others 1 0 1 0 1 0 0.1Hz 1 2 3 10 20 TBD Frequency Acquisition and Bandwidth Track for PLL2 (FB2) - address 17h FB2 register determines bandwidth for Secondary PLL in frequency acquisition and tracking modes. The tables below represent available combinations for B0-B3 (frequency acquisition) and F0-F3 (tracking). B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 The default value: FB2: 0x53h. B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bandwidth NA 10Hz 20Hz 30Hz 40Hz 50Hz 60Hz 70Hz 80Hz 90Hz 100Hz 200Hz 300Hz 400Hz 500Hz 600Hz F3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 F2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 F1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 F0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bandwidth NA 3Hz 5Hz 10Hz 15Hz 20Hz 25Hz 30Hz 35Hz 40Hz 50Hz 60Hz 70Hz 80Hz 100Hz 200Hz SPI Status Register (SST) - address 18h The SST register represents current status of SPI communication. The address can be read only one of the following values: MESSAGE SPIERRSTATOK SPIERRRECOVERFLOW SPIERRINVALIDADDR SPIERRINVALIDWRITEADDR VALUE 0 2 3 4 ACTION If correct command was received by the module If more then two bytes are received before the routine handled If incorrect address was received by the module If incorrect write address or value was received by the module Customer ID Register (CID) - address 19h The CID register contains unique customer identification number. The default value: CID: 0x03h. Software ID Register (SID) - address 1Ah The SID register contains unique software identification number. RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 17 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 The default value: SID: 0x18h. (will vary with new updates) The Standard Timing Application in Systems A typical timing application for telecommunication equipment is shown at the figure below. The system consists of two Clock Cards (CC1 and CC1) and several Line Cards (LC 1 to LC N). The Clock Cards use two clock modules SY10 to generate two redundant signal references for the whole box and the Line Cards use high frequency synchronizer module SY05 as a high frequency reference signals for communication ICs (for e.g. transceivers). The two Clock Cards are connected in such a way to provide a Master/Slave operation of two clocks. At CC the local processors can configure and monitor SY10 module by serial port SPI. Two reference signals and optionally four status signals from each Clock Card (STATUS 1 and STATUS 2) are distributed to all Line Cards. The STATUS 1 and 2 signals are HOLDOVER (pin 1 at SY10), FREERUN (pin 7), ALARM OUT (pin 11) and PLL UNLOCK (pin 17) and they are connected to the corresponding pins at SY05 modules. For a particular application or a timing application that best fits to you please contact Raltron. HF OUT 1 SY05 1 LC 1 STATUS 1 HF OUT 2 SERIAL PORT SY10 1 OUT (10) SEC IN (25) SY05 2 LC 2 CC 1 SEC IN (25) SERIAL PORT SY10 2 OUT (10) CC 2 STATUS 2 HF OUT N SY05 N LC N Figure 9. A typical timing application. RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 18 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 * SPECIFICATIONS Mechanical Power Supply Warm Up Current Supply Steady State Current Supply Operating Temperature Humidity Internal Oscillators Input Signals Number of Inputs Input reference frequency Signal Level Time Reference characteristics Number of Outputs Output 1 Output 2 Output 3 Signal Level I/O Jitter Tolerance Phase Transient Tolerance Wander Generation Wander Tolerance Jitter Generation and Transfer Wander Transfer Frequency Output Performance Free run accuracy Holdover frequency stability Initial Offset Temperature Drift Phase Build-Out DPLL bandwidth Lock Time Lock accuracy Stratum 3E 4.6ppm 1x10-8 /24 h 1x10-9 8x10-9 1x10-9 Yes 0.001Hz <700 1x10-11 Stratum 3 4.6ppm 0.37x10-6 /24 h 50x10-9 280x10-9 1x10-9 No 0.1Hz <100sec 1x10-11 Bellcore: GR-1244-core 5.2 ITU-T: G.812 Bellcore: GR-1244-core 5.7 ITU-T: G.812 or adjustable up to 20Hz GR-1244-core 3.5 GR-1244-core 5.1 ITU-T: G.812 Bellcore: GR-1244-core 5.2 ITU-T: G.812 Bellcore: GR-1244-core 5.2 ITU-T: G.812 1.82" (D) x 1.82" (W) x 0.70" (H) 1.8" (D) x 1.8" (W) x 0.60" (H) 3.3VDC 700mA max @ 25C 400mA max. @ 25C -20C to 70C 5% to 95% non-condensing OCXO 6 8kHz to 77.76MHz HCMOS/TTL Compatible 3 8KHz to 77.76MHZ 8KHz to 77.76MHZ 8KHz HCMOS Metal box Module on PCB Varies from different oscillator used Other ranges available on request SC-cut for Stratum 3E AT-cut for stratum 3 User selectable Bellcore: GR-1244-core 3.2.1.R3-1 User define User define 3.3V levels 5V tolerant Bellcore: GR-1244-core 4.2 ITU-T: G.813 Bellcore: GR-1244-core 4.4 Bellcore: GR-1244-core 5.3 ITU-T: G.812 Bellcore: GR-1244-core 4.3 ITU-T: G.812 Bellcore: GR-1244-core 5.5 ITU-T: G.812 Bellcore: GR-1244-core 5.4 ITU-T: G.812 General Specifications Output Signal Signal Quality Performance RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 19 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 * PIN ASSIGNMENT VCC EX REF 5 EX REF 1 EX REF 3 GND EX REF 6 EX REF 2 EX REF 4 GND SEC IN OPT OUT1 DIN GND SCLK OUT DOUT GND 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 HOLDOVER REF 3 REF 1 REF 4 REF 2 REF 5 FREERUN REF 6 GND M/S OUT ALARM OUT OPT OUT2 CNT 1 CNT 3 CNT 2 MS/FR PLL UNLOCK Figure 10 - Bottom view Pin # 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 9,18,22,26,30 34 19 20 21 23 24 25 27 28 29 31 32 33 Name HOLDOVER REF 3 REF 1 REF 4 REF 2 REF 5 FREERUN REF 6 M/S OUT ALARM OUT OPT OUT2 CNT 1 CNT 3 CNT 2 MS/FR PLL UNLOCK GND VCC DOUT OUT SCLK DIN OPT OUT1 SEC IN EX REF 4 EX REF 2 EX REF 6 EX REF 3 EX REF 1 EX REF 5 Description Holdover Signal -> the output is high when the unit is in holdover mode Reference 3 Signal -> See Indication section on page 4 Reference 1 Signal -> See Indication section on page 4 Reference 4 Signal -> See Indication section on page 4 Reference 2 Signal -> See Indication section on page 4 Reference 5 Signal -> See Indication section on page 4 Free-run Signal -> the output is high when the unit is in the free run mode Reference 6 Signal -> See Indication section on page 4 Master/Slave Synchronizing output (To be connected to slave module SEC-IN Alarm signal -> the output is high when there is an alarm in the module. Optional Output 2-> the secondary output of the synchronized signal Control Input 1 -> the external input for selecting mode of the unit - see table. Control Input 3 -> the external input for selecting mode of the unit - see table. Control Input 2 -> the external input for selecting mode of the unit - see table. Master/Slave Selection or Frame SPI Input -> to select master or slave - master/ slave operation of two clocks or in case of using SPI it is Frame synch signal for communication. PLL Unlocked Signal -> the output is high when the unit is not locked to any of the references Ground Positive Voltage Supply Serial Data Output -> SPI serial communication interface data output Synchronized Output -> the output of the synchronized signal Serial Clock Input -> SPI serial communication interface clock input Serial Data Input/ -> SPI serial communication interface data input Optional Output 1-> the secondary output of the synchronized signal,. SEC Input -> the input from the second clock module - master/slave operation of two clocks. External Reference 4 Input -> the input signal from reference 4 External Reference 2 Input -> the input signal from reference 2 External Reference 6 Input -> the input signal from reference 6 External Reference 3 Input -> the input signal from reference 3 External Reference 1 Input -> the input signal from reference 1 External Reference 5 Input -> the input signal from reference 5 RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com 20 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT - SY10 * MECHANICAL DIMENSIONS 1.82 SQ. (46.23 SQ.) .440 (11.18) .085 (2.16) 1.60 (40.64) C L 34 1 MARKING AREA 1.700 (43.18) .100 C (2.54) L 18 17 .065 (1.65) .076 (1.93) (4 PLCS) .910 .200 (5.08) .210 (4.57) .100 (2.54) 1.400 .005 (35.56 .127) PCB Figure 11 - The mechanical dimensions. Figure 11 shows the mechanical dimension of the SY10 module. The module can be supplied in two different types of packaging: Metal box Module without packaging The label on the module shows part number, factory name, week and year of production. Without metal cover maximum height reaches 0.60". RALTRON ELECTRONICS CORP. ! 10651 N.W.19th St ! Florida 33172 ! U.S.A. Tel: 305 593-6033 ! Fax: 305-594-3973 ! e-mail: sales@raltron.com ! Internet: http://www.raltron.com .071 (1.82) NOTES: UNLESS OTHERWISE SPECIFIED, ALL TOLERANCES ARE: .005 (.127 mm). .910 (23.11) .030 (0.76) 1 .060 (4 PLCS) (1.52) .630 (16.00) 21 |
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